diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
index a37ed16..4839c94 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -12,6 +12,13 @@
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 	/* XECS1: sub/boot memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
index af44dee..5efee9c 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
@@ -12,6 +12,13 @@
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 #if !defined(CONFIG_SPL_BUILD)
 	/* XECS0 : dummy */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
index 8e41078..efb68e8 100644
--- a/arch/arm/include/asm/arch-uniphier/sbc-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
@@ -95,6 +95,7 @@
 #define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
 #define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
 
+#define PC0CTRL				0x598000c0
 #define ROM_BOOT_ROMRSV2		0x59801208
 
 #ifndef __ASSEMBLY__